Once a model has undergone quantization, either through QAT or PTQ, and its low-precision operations are represented in the compiler's IR, the next significant step is translating these representations into highly efficient machine code. This code generation phase is critical; it must effectively utilize the specialized low-precision capabilities offered by modern hardware, such as CPUs with advanced SIMD extensions, GPUs with Tensor Cores or Matrix Cores, and dedicated AI accelerators. Simply performing computations using smaller data types isn't sufficient; achieving performance gains requires generating code that leverages specific hardware instructions designed for accelerated low-precision arithmetic.

Mapping Quantized Operations to Hardware Instructions

High-level quantized operations, often represented using dedicated dialects or attributes in the IR (as discussed in "Representing Quantized Operations in IR"), need to be lowered into sequences of target-specific instructions. This process involves more than just replacing floating-point operations with integer or low-precision floating-point ones. It must also correctly handle the associated quantization parameters (scales and zero points).

Consider a common operation like an INT8 matrix multiplication followed by requantization to INT8 output. Conceptually, the core computation might involve accumulating products in a wider integer format, typically 32-bit integers ( $INT32$ ), to prevent overflow:

Acc_{int32} = \sum (A_{int8} - A_{zp}) \times (B_{int8} - B_{zp})

Here, $A_{int8}$ and $B_{int8}$ are the input operands, and $A_{zp}$ , $B_{zp}$ are their respective zero points. Many hardware instructions implicitly handle or assume zero-centered inputs, requiring the compiler to sometimes adjust the computation or zero points accordingly.

After the accumulation, the result ( $Acc_{int32}$ ) needs to be rescaled and potentially shifted by the output zero point ( $C_{zp}$ ) to produce the final INT8 output ( $C_{int8}$ ). This often involves a multiplication by a fused scale factor (derived from $Scale_A$ , $Scale_B$ , and $Scale_C$ ) and potentially a right shift for fixed-point arithmetic, followed by clamping to the valid INT8 range [-128, 127]:

C_{int8} = \text{clamp}(\text{round}(Acc_{int32} \times \text{FusedScale}) + C_{zp})

The compiler's task is to map this entire sequence, including operand loading, zero-point adjustments (if necessary), the core multiply-accumulate operation, and the final requantization step, onto the most efficient available hardware instructions.

Leveraging Specialized Hardware Instructions

Modern processors include instructions specifically designed to accelerate low-precision computations. Effective code generation hinges on identifying and utilizing these instructions.

Integer Instructions (INT8, INT4)

CPUs: Architectures like Intel x86 with AVX512-VNNI (Vector Neural Network Instructions) provide instructions like VPDPBUSD which performs a dot product on four pairs of 8-bit unsigned and signed integers, accumulating the result into a 32-bit integer, all within a single instruction operating on wide vector registers. Similarly, ARM Neon offers dot product instructions (SDOT, UDOT) for accelerating INT8/UINT8 computations. Compilers must pattern-match computation sequences in the IR to emit these powerful instructions.
GPUs: NVIDIA GPUs starting from Volta feature Tensor Cores, which perform matrix-multiply-accumulate operations on small matrices (e.g., $4 \times 4$ or $16 \times 8 \times 16$ ) of FP16, BF16, TF32, INT8, or even INT4/FP8 data types in a single cycle. For INT8, instructions like IMMA (Integer Matrix Multiply Accumulate) operate on tiles of integer data, accumulating into INT32 registers. AMD's CDNA architecture includes Matrix Core Engines performing similar matrix operations for low-precision types. Generating code for these units requires structuring loops and data layouts to feed these matrix units efficiently.
AI Accelerators: Custom ASICs (like Google TPUs, Apple Neural Engine) often feature large systolic arrays or matrix multiplication units optimized specifically for low-precision integer (primarily INT8) arithmetic. Compilation for these targets involves mapping tensor operations directly onto these hardware units, managing data flow through local memory buffers, and orchestrating the systolic array execution.

Low-Precision Floating-Point Instructions (FP8)

Emerging hardware, such as NVIDIA's Hopper architecture (H100 GPU) and AMD's MI300, introduces support for 8-bit floating-point formats (FP8), typically E4M3 (4-bit exponent, 3-bit mantissa) and E5M2 (5-bit exponent, 2-bit mantissa).

Hardware Support: These formats offer a compromise between the range of FP16 and the efficiency of INT8. Hopper GPUs, for example, include specialized mma (matrix-multiply-accumulate) instructions that operate directly on FP8 data, often using FP32 accumulators for improved numerical stability.
Compiler Challenges: Generating code for FP8 presents unique challenges:
- Format Conversion: Explicit instructions or compiler passes are needed to convert between FP32/FP16 and the target FP8 format (E4M3 or E5M2).
- Scaling: FP8 formats have a very limited dynamic range. Numerical stability often requires careful scaling factors (similar to quantization scales) managed by the compiler or runtime. These scales might need to be applied dynamically.
- NaN/Inf Handling: The reduced exponent bits impact the handling of special values.
- Instruction Mapping: Compilers need specific backends to target the new FP8 mma instructions, structuring computation into appropriate matrix tile sizes.

Code Generation Strategies for Low Precision

Generating efficient low-precision kernels requires adapting existing compiler optimization techniques and introducing new ones tailored for these data types and hardware features.

Instruction Selection: The compiler backend must possess detailed knowledge of the target architecture's low-precision instruction set (e.g., VNNI, IMMA, FP8 mma). Pattern matching is used to identify opportunities in the IR to replace sequences of simpler operations with these more powerful, specialized instructions.
Register Allocation: Low-precision operations often involve mixed-precision aspects (e.g., INT8 multiply with INT32 accumulate). Register allocators must manage different register file types (vector, matrix, scalar) and handle the potentially larger accumulator registers efficiently. The pressure on registers can increase, especially when tiling for matrix units.
Loop Tiling and Vectorization: Standard loop tiling (Chapter 4) is essential but must be adapted. Tile sizes should be chosen to match the dimensions expected by the hardware's low-precision matrix units (e.g., tiling a matrix multiplication loop to operate on $16 \times 8$ blocks of $A$ and $8 \times 16$ blocks of $B$ for a target using $16 \times 8 \times 16$ MMA instructions). Vectorization targets SIMD instructions like VNNI or Neon dot products.
Requantization/Dequantization Optimization: The code for scaling, shifting, and clamping during requantization or dequantization can introduce overhead. Compilers attempt to:
- Fuse these operations with the preceding compute kernel.
- Vectorize the scaling and clamping steps.
- Utilize specialized hardware instructions if available for these conversions.
- Minimize the frequency of these operations, for instance, by keeping intermediate results in the accumulator precision (e.g., INT32) across fused operator sequences.
Memory Layout: Data layout transformations (e.g., NCHW vs. NHWC vs. more specialized tiled layouts like NCHWc[x]) become even more important. Layouts should facilitate contiguous access for vector instructions and efficient loading into matrix units. Some hardware requires specific memory layouts for optimal performance with low-precision units.

Theoretical peak throughput increase for different precisions and hardware units relative to baseline FP32 performance. Actual speedup depends heavily on memory bandwidth, kernel implementation, and problem size.

Compiler Backend Integration

The process of generating low-precision code is typically handled in the compiler backend.

IR Representation: High-level ML dialects are lowered through intermediate dialects (like MLIR's linalg, vector, arith) where quantized types and operations are still explicitly represented.
Lowering to Target Intrinsics: Target-specific passes lower these operations further, often generating target-specific IR constructs or directly emitting LLVM intrinsics (or other backend IR intrinsics) that correspond to the hardware's low-precision instructions (e.g., @llvm.x86.avx512.vpdpbusd, NVIDIA PTX mma instructions).
Final Code Generation: The backend's instruction selector maps these intrinsics to machine instructions, performs register allocation considering the target's capabilities, and schedules the instructions.

Successfully generating high-performance low-precision kernels requires a deep integration between the compiler's optimization passes and its knowledge of the target hardware's specialized units and instruction sets. It transforms the abstract notion of "using INT8" into concrete, efficient machine code that delivers the desired performance benefits on modern hardware.